1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor apparatus.
2. Related Art
In general, as the capacity of a DRAM (dynamic random access memory) increases, the resistance of lines increases, and thus, it becomes necessary to optimize delay time by appropriately controlling the lengths of the lines. To this end, word lines for selecting rows of a memory cell array are appropriately controlled. Thus, in a contemporary semiconductor memory apparatus, a hierarchical word line driving mechanism has been adopted, in which word lines are controlled to have appropriate lengths to form sub word lines.
To this end, word lines are made from a plurality of main word lines and a plurality of sub word lines which are coupled in common to each main word line. The sub word lines are coupled respectively to a mat which includes a plurality of memory cells.
Usually only a single sub word line is activated by an address, and an even word line driver and an odd word line driver are respectively disposed on both sides of a cell array (hereinafter referred to as a “mat”).
A sub word line signal, which is activated by each sub word line driver, activates a plurality of memory cells, and a voltage difference (hereinafter referred to as “charge sharing”) is induced between a bit line and a bit line bar. A bit line sense amplifier senses and amplifies the induced voltage difference in response to a sense amplifier enable signal, by which a data read operation is performed.
For example, assuming that an odd sub word line is activated, charge sharing between a bit line and a bit line bar occurs early near an odd word line driver and later near an even word line driver.
In a semiconductor apparatus, since the sense amplifier enable signal should be activated so as to cover where the charge sharing occurs latest to activate the bit line sense amplifier, the sense amplifier enable signal is delayed due to resistive and capacitive components of a metal line.
When a sense amplifier enable signal is activated at the same time on both sides of the mat, sense amplifiers in the middle region of the mat operate latest.
In the conventional semiconductor apparatus, charge sharing by word lines occurs latest near the even and odd word line drivers, that is, on both sides of the mat, and sense amplifiers in the middle region of the mat operate latest. Thus, data is sensed latest in the middle region of the mat.
Accordingly, in the conventional semiconductor apparatus, limitations exist in increasing a data processing speed.